Lock in pinned photodiode photodetector

ABSTRACT

A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/378,565, filed Aug. 19, 1999 (allowed), which claims thebenefit of the U.S. Provisional Application No. 60/097,135, filed onAug. 19, 1998, which is incorporated herein by reference.

BACKGROUND

[0002] Certain applications require measuring aspects that are based onthe speed of light.

[0003] For example, range finding can be carried out using optics. Anoptical signal is sent. The reflection therefrom is received. The timethat it takes to receive the reflection of the optical signal gives anindication of the distance.

[0004] The so called lock-in technique uses an encoded temporal patternas a signal reference. The device locks into the received signal to findthe time of receipt. However, noise can mask the temporal pattern.

[0005] A lock in photodetector based on charged coupled devices or CCDshas been described in Miagawa and Kanada “CCD based range findingsensor” IEEE Transactions on Electronic Devices, volume 44 pages1648-1652 1997.

[0006] CCDs are well known to have relatively large power consumption.

SUMMARY

[0007] The present application describes a special kind of lock indetector formed using CMOS technology. More specifically, a lock indetector is formed from a pinned photodiode. The photodiode is modifiedto enable faster operation.

[0008] It is advantageous to obtain as much readout as possible tomaximize the signal to noise ratio. The pinned photodiode providesvirtually complete charge transfer readout.

[0009] Fast separation of the photo-generated carriers is obtained byseparating the diode into smaller sub-parts and summing the outputvalues of the subparts to obtain an increased composite signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These an other aspects will now be described in detail withreference to the accompanying drawings, wherein:

[0011]FIG. 1 shows a basic block diagram of the system;

[0012]FIG. 2 shows a block diagram of the multiple photodiode parts;

[0013]FIG. 3 shows a block diagram of the system as used in rangefinding;

[0014]FIGS. 4a and 4 b show pixel layouts; and

[0015]FIG. 5 shows a cross section of the pinned photodiode.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0016] The present application uses a special, multiple output portpinned photodiode as the lock in pixel element. The photodiode ispreferably part of a CMOS active pixel image sensor, of the typedescribed in U.S. Pat. No. 5,471,505. Hence, the system preferablyincludes in-pixel buffer transistors and selection transistors, inaddition to the CMOS photodetector.

[0017]FIG. 1 shows a pinned photodiode with four output ports, labeledas out1-out4. Each of the output ports is used to receive a reflectionfor a specified time duration. Each output becomes a “bin”. The countingof the amount of information in the bins enables determination of thereflection time, and hence the range.

[0018] Pinned photodiodes are well known in the art and described inU.S. Pat. No. 5,904,493. A pinned photodiode is also known as a holeaccumulation diode or HAD, or a virtual phase diode or VP diode.Advantages of these devices are well known in the art. They have smalldark current due to suppression of surface generation. They have goodquantum efficiency since there are few or no polysilicon gates over thephotosensitive region. Pinned photodiodes can also be made into smallerpixels because they have fewer gates.

[0019] The basic structure of the pinned photodiode lock in pixel isshown in FIG. 1. Four switched integrators are formed respectively atfour output ports. Each gate is enabled during a specified period. Thedifferent integrators integrate carriers accumulated during thedifferent periods. The first integrator accumulates carriers between 0and π/2, the second between π/2 and n, the third between π and 3π/2 andthe fourth between 3π/2 and 2π time slots.

[0020] Assuming the light to be a cosine phase, then the phase shift ofthe detected light is given by

arctan[(L 1−L 3)/(L 2−L 4)],

[0021] where L1, L2, L3 and L4 are the amplititudes of the samples fromthe respective first, second, third and fourth integrators. These fourphases are obtained from the four outputs of the photodiode.

[0022] The first pinned photodiode 100 is connected to an output drain102 via gate 1, element 104. This receives the charge for the first bin.Similarly, gates 2, 3 and 4 are turned on to integrate/bin from thesecond, third and fourth periods.

[0023] It is important to obtain as much signal as possible from thephotodiode. This can be done by using a large photodiode. However, itcan take the electrons a relatively long time to escape from a largephotodetector.

[0024] The present system divides the one larger photodiode into anumber of smaller diodes, each with multiple output ports. FIG. 2 showsthe system.

[0025] A number of subpixels are formed. Each includes a number ofpinned photodiodes 200, each with four ports. Each of the correspondingports are connected together in a way that allows summing the outputs ofthe photodiodes. For example, all the gate 1 control lines are connectedtogether as shown. The outputs from all the port is are also summed, andoutput as a simple composite output. Similarly, ports 2, 3 and 4's areall summed.

[0026]FIG. 3 shows the circuit and driving waveforms for the system whenused as a range finder. A pulse generator drives selection of the activeoutput. Each time period is separately accumulated, and output. If a 40MHZ pulse generator is used, 25 ns resolution can be obtained.

[0027]FIGS. 4A and 4B show representative pixel layouts. FIG. 4A shows a6 by 6 square micron pixel layout while FIG. 4B shows an 8½ by 8½ micronpixel layout. In both Figures, four outputs are shown.

[0028]FIG. 5 shows a cross sectional potential diagram of an exemplarypinned photodiode.

[0029] Assuming the operation frequency of modulated light is 10megahertz with a 25 nanosecond integration slot, the generator carrierhas a time of flight within this limit. This resolution time constrainsthe size of the detector. In addition, the characteristic diffusion timein a semiconductor device is L²/D, where D is the diffusion coefficient.This time originates from the continuity equation and the diffusionequation, and defines how soon the steady state will be established inthe area of size L. Hence, for a 10 cm square per second electrondiffusion coefficient, the characteristic size of the pinned photodiodecould be less than 5 microns.

[0030] Other embodiments are also contemplated to exist within thisdisclosure. For example, other numbers of output ports, e.g. 2-8, arepossible. While this application describes using a pinned photodiode,similar operations could be carried out with other CMOS photodetectors,e.g., photodiodes and photogates.

[0031] Such modifications are intended to be encompassed within thefollowing claims.

What is claimed is:
 1. A lock-in photo-detector.